1. Field of the Invention
The present invention relates to memory test circuits for performing tests of semiconductor memories, and particularly to a memory test circuit for performing tests of Random Access Memories (referred to as RAM, hereinafter) using ping-pong pattern.
2. Description of the Background Art
Input/output pins of a RAM provided in an application specific IC (ASIC) etc. are usually connected to a logic portion, from which signals are provided to the RAM, so that tests can not be applied directly to the RAM using external pins. FIG. 8 shows a configuration of a chip in which a memory test circuit for performing tests of RAM is provided in the chip to enable tests of a built-in RAM. Here, the memory test circuit built in the chip 1 is referred to as a RAM-BIST (Built In Self Test) circuit.
In the normal operation, that is, when a test pin 8 is supplied with "0" as a signal RAM-TEST, data inputted from external input pins 3 are processed in a logic portion 5 and then the processed data is provided to a RAM 2. Data outputted from the RAM 2 is provided to a logic portion 6. Data processed in the logic portion 6 is externally outputted from external output pins 4.
When the signal RAM-TEST provided to the test pin 8 is at "1", input pins of the RAM 2 built in the chip 1 are separated from the logic portion 5 by a selector circuit 9 and the RAM 2 is tested by a RAM-BIST circuit 7. The RAM-BIST circuit 7 performs functions of generating test patterns, comparing tested outputs and expected values, compressing test results, etc. This RAM-BIST circuit 7 generates various address patterns to test the RAM.
Next, a description will be made on generation of address patterns in the RAM-BIST circuit 7 referring to FIG. 9. FIG. 9 is a block diagram for describing a configuration of an address pattern generating circuit provided in the RAM-BIST circuit 7 shown in FIG. 8 for generating ping-pong pattern which is a kind of test pattern. In FIG. 9, 2A denotes a RAM in which memory cells are selected with 4-bit address input signals A0, A1, A2, A3, 10 denotes a first counter, 11 denotes a second counter, and 12 denotes a selector circuit for selectively outputting one of the first and second counters to the RAM 2A in accordance with a selection signal sel.
The ping-pong pattern is a test pattern with very high detecting ability. The algorithm of a memory test according to the ping-pong pattern will now be described. First, the RAM-BIST circuit 7 writes "0" into all memory cells in the RAM 2A. Next, it writes "1" into a remarked memory cell, a memory cell at the address "0000", for example. Then, the RAM-BIST circuit 7 performs read operation according to the ping-pong pattern in the order of address 1, address 0, address 2, address 0, address 3, address 0, . . . address 0, address N, for example. In the ping-pong pattern, "0" is written in the address 0, and if a remarked cell is the address 1, for example, "1" is written in the address 1, and the same operation as that described above is performed about the remarked cell. That is to say, reading is carried out in the order of address 0, address 1, address 2, address 1, address 3, address 1, . . . address 1, address N. Then, "0" is written into address 1. In the ping-pong pattern, the remarked cell is shifted to the address N, and the operation of alternately reading the remarked cell and other cells as described above is performed every time "1" is written into a remarked cell.
A conventional circuit for generating address pattern according to the ping-pong pattern includes a second counter 11 for generating address signals for remarked cells and a first counter 10 for generating address signals for other cells, which is configured so that outputs of the two counters 10 and 11 are switched by the selector circuit 12 for every cycle.
The EN0 and EN1 are control signals for stopping operations of the first and second counters, respectively.
The control signals EN0 and EN2 control so that the first counter 10 operates for every cycle of clock, and the second counter 11 operates for every (the number of addresses of a tested circuit.times.2 cycles), in the case of the test of the RAM 2A shown in FIG. 8, every 4.times.2 cycles, respectively. The selector circuit 12 is controlled by the selection signal sel to switch outputs of the first counter 10 and the second counter 11 every cycle.
Next, a counter circuit forming the RAM-BIST circuit 7 will be described. FIG. 10 is a logic diagram showing a configuration of a 4-bit counter. In FIG. 10, 15-18 denote flip-flops which operate in synchronization with a clock T, 19 denotes an NOT gate for providing a negation of output of the flip-flop 15 to the input terminal of the flip-flop 15, 20 denotes an EXCLUSIVE-OR gate (referred to as an XOR gate, hereinafter) for applying "1" to the input terminal of the flip-flop 16 when the output of the flip-flop 15 and the output of the flip-flop 16 differ, 21 denotes an AND gate for outputting "1" when outputs of the flip-flops 15 and 16 are both "1", 22 denotes an AND gate for outputting "1" when the output of the AND gate 21 and the output of the flip-flop 18 are both "1", 23 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 17 when the output of the AND gate 22 and the output of the flip-flop 17 differ and 24 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 18 when the output of the flip-flop 18 and the output of the AND gate 21 differ.
In order to operate as a counter, the circuit shown in FIG. 10 provides outputs DO&lt;*&gt; of the flip-flops as input data DI&lt;*&gt; so that the numbers enclosed in &lt;&gt; are equal.
FIG. 11 is a logic diagram showing a configuration of a 10-bit counter. The counter shown in FIG. 11 is formed for the purpose of decreasing the occupied area without attaching importance to the operating speed. In FIG. 11, 30-39 denote flip-flops operating in synchronization with a clock T, 40 denotes an NOT gate for providing a negation of the output of the flip-flop 30 to the input terminal of the flip-flop 30, 41 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 31 when the output of the flip-flop 30 and the output of the flip-flop 31 differ, 42 denotes an AND gate for outputting "1" when the output of the flip-flop 30 and the output of the flip-flop 31 are both "1", 43 denotes an AND gate for outputting "1" when the output of the AND gate 42 and the output of the flip-flop 39 are both "1", 44 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 32 when the output of the flip-flop 32 and the output of the AND gate 43 differ, 45 denotes an NAND gate for outputting "0" when the output of the flip-flop 32, the output of the AND gate 43, and the output of the flip-flop 34 are all "1", 46 denotes an NOT gate for outputting a negation of the output of the flip-flop 33, 47 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 33 when the output of the NOT gate 46 and the output of the NAND gate 45 differ, 48 denotes an AND gate for outputting "1" when the output of the flip-flop 32 and the output of the AND gate 43 are both "1", 49 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 34 when the output of the flip-flop 34 and the output of the AND gate 48 differ, 50 denotes an OR gate for outputting "1" when either one of the output of the NAND gate 45 and the output of the NOT gate 46 is "1", 51 denotes an NOT gate for outputting a negation of the output of the flip-flop 37, 52 denotes an NOR gate for outputting "0" when either one of the output of the OR gate 50 and the output of the NOT gate 51 is "1" , 53 denotes an AND gate for outputting "1" when the output of the NOR gate 52 and the output of the flip-flop 36 are both "1", 54 denotes an AND gate for outputting "1" when the output of the AND gate 53 and the output of the flip-flop 38 are both "1", 55 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 35 when the output of the flip-flop 35 and the output of the AND gate 54 differ, 56 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 36 when the output of the NOR gate 52 and the output of the flip-flop 36 differ, 57 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 37 when the output of the NOT gate 51 and the output of the OR gate 50 differ, 58 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 38 when the output of the flip-flop 38 and the output of the AND gate 53 differ, and 59 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 39 when the output of the flip-flop 39 and the output of the AND gate 42 differ.
To operate as a counter, the circuit shown in FIG. 11 provides the outputs DO&lt;*&gt; of the flip-flops as the input data DI&lt;*&gt; so that the numbers enclosed in the &lt;&gt; are equal.
FIG. 12 is a logic diagram showing a configuration of a 10-bit counter operating at higher speed than the 10-bit counter shown in FIG. 11. In FIG. 12, 60-69 denote flip-flops operating in synchronization with the clock T, 70 denotes an NOT gate for applying a negation of the output of the flip-flop 69 to the input terminal of the flip-flop 69, 71 denotes an NAND gate for outputting "0" only when the outputs of the flip-flops 65, 66, 69 are all "1", 72 denotes an NOT gate for performing Boolean operation for negating the output of the NAND gate 71 and outputting its result, 73 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 68 when the output of the flip-flop 68 and the output of the NOT gate 72 differ, 74 denotes an AND gate for outputting "1" when the output of the flip-flop 68 and the output of the flip-flop 64 are both "1", 75 denotes an AND gate for outputting "1" when the outputs of the NOT gate 72 and the AND gate 74 are both "1", 76 denotes an AND gate for outputting "1" when the outputs of the flip-flops 60, 62 are both "1", 77 denotes an AND gate for outputting "1" when the outputs of the AND gates 75, 76 are both "1", 78 denotes an NOT gate for outputting a result of Boolean operation for negating the output of the flip-flop 67, 79 denotes an NAND gate for outputting "0" only when the output of the AND gate 77 and the output of the flip-flop 61 are both "1", 80 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 67 when the output of the NOT gate 78 and the output of the NAND gate 79 differ, 81 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 66 when the outputs of the flip-flops 66, 69 differ, 82 denotes an AND gate for outputting "1" when the outputs of the flip-flops 66, 69 are both "1", 83 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 65 when the output of the flip-flop 65 and the output of the AND gate 82 differ, 84 denotes an AND gate for 25 outputting "1" when the output of the flip-flop 68 and the output of the NOT gate 72 are both "1", 85 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 64 when only one of the output of the flip-flop 64 and the output of the AND gate 84 is "1", 86 denotes an NOR gate for outputting "0" when either one of the output of the NAND gate 79 and the output of the NOT gate 78 is "1", 87 denotes an NOT gate for outputting a result of Boolean operation of negation of the output of the flip-flop 63, 88 denotes a selector receiving the output of the flip-flop 63 and the output of the NOT gate 87 as inputs for outputting the output of the NOR gate 86 as a select signal to the input terminal of the flip-flop 63, 89 denotes an AND gate for outputting "1" when the output of the flip-flop 60 and the output of the AND gate 75 are both "1", 90 denotes an XOR gate for outputting "1" to the input terminal of the flip-flop 62 when the output of the AND gate 89 and the output of the flip-flop 62 differ, 91 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 61 when the output of the flip-flop 61 and the output of the AND gate 77 differ, and 92 denotes an XOR gate for applying "1" to the input terminal of the flip-flop 60 when the output of the flip-flop 60 and the output of the AND gate 75 differ.
To operate as a counter, the circuit shown in FIG. 12 provides the outputs DO&lt;*&gt; of the flip-flops as the input data DI&lt;*&gt; so that the numbers in &lt;&gt; are equal.
Operation of the selector 88 is shown in Table 1.
TABLE 1 ______________________________________ Negation of Output of D output of D Output of NOR Output of flip-flop 62 flip-flop 62 gate 86 selector 88 ______________________________________ H x H L L x H H x H L L x L L H ______________________________________
In the conventional memory test circuit configured as described above, two counters are used in a memory test pattern generating circuit provided in the memory test circuit for generating the ping-pong pattern which is a kind of memory test pattern. The counters are complicated in structure and slow in operation, causing a problem of enlarged scale and slow speed of the memory test circuit.
The problem becomes more serious as the number of bits of the RAM increases, as the scale of the structure of the 10-bit counter becomes more complicated and larger as compared with the 4-bit counter shown in FIG. 10, not in proportion to the increase in number of bits.
Furthermore, as the number of addresses of a tested circuit increases, a counter with a higher speed is required for addressing in the real operation of the tested circuit, which causes a problem of a further increase in scale of the circuit, as can be clearly seen by comparing the counters shown in FIG. 11 and FIG. 12.